Fail-safe timing circuit and on-delay circuit using the same

ABSTRACT

The present invention relates to a fail-safe timing circuit and on-delay circuit which does not produce an erroneous output where the delay time is shortened, due to a fault. The timing circuit comprises: an oscillation circuit ( 11 ) which produces a timing output from a cathode terminal of a PUT after a predetermined time lapse from input of an input signal (V IN ); and a monitoring circuit ( 12 ) for monitoring for the normalcy of the oscillation circuit ( 11 ). Moreover the on-delay circuit comprises a self hold circuit ( 13 ) with an output signal (Vo) generated from the monitoring circuit ( 12 ) only when the normalcy of the oscillation circuit ( 11 ) is verified by generation of a falling signal of a cathode terminal voltage of the oscillation circuit ( 11 ), input to a second terminal (b), and the input signal (V IN ) input to a first terminal (a), which produces an output signal only when the two input signals are both at a higher level than a power source potential.

TECHNICAL FIELD

The present invention relates to a fail-safe timing circuit in which atiming interval is not shortened at the time of a fault, and to afail-safe on-delay circuit which utilizes such a timing circuit so thatthe delay time is not shortened at the time of a fault.

BACKGROUND ART

With a fail-safe on-delay circuit, an error wherein the delay time isshortened due to a fault is not permitted. Heretofore, with on-delaycircuits it has been common to use a counter circuit as a timing circuitfor setting the delay time. With a counter circuit however there areproblems for example in that the frequency of the clock signal used fortiming can increase with a malfunction so that the delay time isshortened, or that if the circuit faults, an output signal can begenerated although an input signal is not being applied.

In order to solve such problems, there has been proposed (JapaneseUnexamined Patent Publication No. 2-141122) a fail-safe on-delay circuitwhich uses in the timing circuit, a PUT oscillation circuit which uses aprogrammable uni-junction transistor (referred to hereunder as PUT). Theconstruction of the fail-safe on-delay circuit is such that a delayoutput is generated on receipt of an output signal from the PUToscillation circuit.

FIG. 15 shows such a conventional basic on-delay circuit which uses aPUT oscillation circuit.

In FIG. 15, the on-delay circuit comprises a PUT oscillation circuit 1,and a self hold circuit 2 which produces an output on receipt of anoutput signal of a predetermined level from the PUT oscillation circuit1, and self holds the output. The PUT oscillation circuit 1 comprises;resistors R₁˜R₄, a capacitor C₁, and a PUT. The self hold circuit 2comprises a logical product circuit 3 having two signal input terminalsa, b, and a rectifying circuit 4 and a feed back resistor Rf for feedingback an output from the logical product circuit 3 to the second terminalb so that the output is self held.

The operation of the on-delay circuit will now be described withreference to the operation time chart shown in FIG. 16.

When an input signal V_(IN) is input to the PUT oscillation circuit 1,then at first, the PUT oscillation circuit 1 becomes condition A. Incondition A, the PUT is off so that the capacitor C₁ of the PUToscillation circuit 1 is gradually charged and the anode terminalvoltage V_(A) rises. Once the capacitor C₁ has been charged to apredetermined voltage level (a gate terminal voltage V_(G)) the PUTcomes on, giving condition B. In condition B, the anode terminal and thecathode terminal, and the gate terminal and the cathode terminal of thePUT are short circuited. Hence the charge stored in the capacitor C₁ isdischarged via the PUT, the anode terminal voltage V_(A) drops, and ananode current i_(A) and a gate current i_(G) flow, producing a cathodecurrent i_(K), so that a cathode terminal voltage V_(K) rises. When therising pulse voltage signal of the cathode terminal voltage V_(K) isinput to the second terminal b of the logical product circuit 3, anoutput signal is produced from the logical product circuit 3 which hasthe input signal V_(IN) already applied to the first terminal a. Thisoutput signal is fed back to the second terminal b via the rectifyingcircuit 4 and the feedback resistor Rf, so that the output signal fromthe logical product circuit 3 is self held. Hence an output signalcontinues to be produced until the input signal V_(IN) is cancelled. Inthis way, an output signal Z is produced from the self hold circuit 2 asa delay output signal for the on-delay circuit, delayed by apredetermined time τ₁ from after applying the input signal V_(IN) to thePUT oscillation circuit 1, based on a timing output signal from the PUToscillation circuit 1.

Once the capacitor C₁ has been discharged to a certain level, the PUTagain goes off, and the PUT oscillation circuit 1 again becomescondition A. While the input signal V_(IN) is being applied, the PUToscillation circuit 1 switches back and forth between condition A andcondition B, while when the input signal V_(IN) is cancelled, the PUToscillation circuit 1 becomes a condition C existing prior to applyingthe input signal V_(IN). In FIG. 15, symbol i_(B2) denotes a biascurrent flowing via the resistor R₄.

With the construction however, as with the conventional on-delay circuitshown in FIG. 15 where after a predetermined time τ₁ from inputting theinput signal V_(IN), only the pulse voltage signal produced at thecathode terminal of the PUT is input directly to the second terminal bof the logical product circuit 3, then if for example during timing, ashort circuit fault occurs between the gate terminal and the cathodeterminal, or between the anode terminal and the cathode terminal of thePUT, an erroneous PUT cathode voltage signal will be produced. There isthus the problem that an erroneous delay output signal is produced, andhence the circuit is not fail-safe. This problem is even mentioned inJapanese Unexamined Patent Publication No. 2-141122.

In Japanese Unexamined Patent Publication No. 2-141122, in order tosolve this problem, the cathode voltage signal and the gate voltagesignal are respectively input to different self hold circuits, and thelogical product output from the two self hold circuits is made the delayoutput signal. With such a circuit configuration, even if during timingafter applying the input voltage V_(IN), a short circuit fault occursbetween the gate terminal and the cathode terminal, there is nogeneration of an erroneous delay output signal. However with the circuitconfiguration of this conventional example, when the input signal V_(IN)is cancelled, a capacitor for continually producing a differentialsignal is charged. Therefore, if the input signal V_(IN) is applied inthe condition with a short circuit fault occurring between the gateterminal and the cathode terminal of the PUT, there can be a problem ofan erroneous delay output signal being produced having practically nodelay time. Moreover there can be a problem in that, under conditionswhere the capacitor for setting the oscillation time constant of the PUToscillation circuit has practically no charge, if a short circuit faultoccurs simultaneously between the anode terminal and the gate terminaland the cathode terminal of the PUT, then when the input signal V_(IN)is applied, the gate voltage signal will initially drop to becomeapproximately a power source potential Vcc, after which it will rise.Therefore depending on the threshold value in an operational oscillatorcomprising a self hold circuit, there is the possibility of an erroneousdelay output signal being produced.

With the circuit of Japanese Unexamined Patent Publication No. 2-141122,there is thus the problem that if a fault occurs in one of theconstituent elements of the circuit, an erroneous delay output can beproduced. Moreover, using two self hold circuits having operationaloscillators causes an increase in cost, and is thus undesirable.

As is clear from the earlier discussion, when the beforementioned PUToscillation circuit is operating normally, it changes from condition Ato condition B and then returns again to condition A, while at the timeof a fault, it remains in condition A or only changes from condition Ato condition B. Therefore using these characteristics of an oscillationcircuit, it is possible to verify if the PUT oscillation circuit isoperating normally,

As a method for verifying normal operation of a PUT oscillation circuitusing these characteristics, it has been considered to use for examplethe signal information of (1) and (2) below:

(1) a characteristic signal (voltage or current) condition produced onlywhen the PUT oscillation circuit is operating normally, that is to saychanges from condition A to condition B and then again to condition A(normal oscillation operation).

(2) a sequential change in the voltage and current condition of thevarious parts of the circuit due to the PUT oscillation circuitoperating normally, that is to say changing from condition A tocondition B and then again to condition A (normal oscillationoperation).

The present invention takes into consideration the above situation withthe object of providing a fail-safe timing circuit which does notproduce an erroneous timing output at the time of a fault, by providinga monitoring circuit for verifying if an oscillation circuit isoperating normally by monitoring a voltage signal change condition whichis based on the operating characteristics of the oscillation circuit.Moreover it is an object of the invention to provide a fail-safeon-delay circuit which does not produce an erroneous delay output at thetime of a fault, by combining a logical product circuit with thefail-safe timing circuit.

DISCLOSURE OF THE INVENTION

Accordingly, the timing circuit of the present invention ischaracterized in comprising: an oscillation circuit which produces anoscillating output using the switching of a switching element, after thelapse of a previously set predetermined time from after applying aninput signal; and a monitoring circuit for monitoring for the normalcyof the oscillation circuit based on electrical operating conditions ofthe oscillation circuit, and generating an output signal only when theoscillation circuit is normal.

With such a construction, an output signal is generated from themonitoring circuit if the oscillation circuit is operating normally.Hence it can be known if the oscillation circuit is normal, from theoutput conditions of the monitoring circuit.

With the timing circuit, the construction may be such that a signal fromthe oscillation circuit, and the input signal are input to themonitoring circuit.

With such a construction, whether or not the input signal is beingapplied to the timing circuit can be verified in the monitoring circuitby a dual system, involving a signal from the oscillation circuit and adirectly input input signal.

With the present invention, the construction may be such that themonitoring circuit monitors for the normalcy of the oscillation circuitbased on a signal change which is produced only when the oscillationcircuit is operating normally, and when the oscillation circuit is a PUToscillation circuit which uses a PUT for the switching element, there isprovided: a differentiating circuit for differentiating a cathodeterminal voltage of the PUT; a photocoupler comprising a photodiode withan anode side connected to a constant voltage line and a cathode sideconnected to an output terminal of the differentiating circuit, and aphototransistor with a collector side connected to the constant voltageline via a resistor, and an emitter side connected to earth; and a levelconversion circuit comprising a capacitor and a diode with the capacitorconnected between an intermediate point between the resistor and thephototransistor and a cathode side of the diode, and an anode side ofthe diode connected to the constant voltage line, and an output signalfrom the level conversion circuit is made the output signal from themonitoring circuit.

With such a construction, a falling change in the cathode voltage of thePUT which is only produced when the oscillation circuit is normal can beverified, and an output signal indicating the normalcy of theoscillation circuit then generated.

Moreover with the present invention, as a concrete configuration forwhere the signal from the oscillation circuit and the input signal areinput to the monitoring circuit, the construction may be such that themonitoring circuit monitors for the normalcy of the oscillation circuitbased on a signal change which is produced only when the oscillationcircuit is operating normally, and when the oscillation circuit is a PUToscillation circuit which uses a PUT for the switching element, there isprovided: a differentiating circuit for differentiating a cathodeterminal voltage of the PUT; a photocoupler comprising a photodiode withan anode side connected to a constant voltage line and a cathode sideconnected to an output terminal of the differentiating circuit, and aphototransistor with a collector side connected via a resistor to aninput signal line to which the input signal is applied, and an emitterside connected to the constant voltage line; and a level conversioncircuit comprising a capacitor and a diode with the capacitor connectedbetween an intermediate point between the resistor and thephototransistor and a cathode side of the diode, and an anode side ofthe diode connected to the input signal line, and an output signal fromthe level conversion circuit is made the output signal from themonitoring circuit.

With such a construction, whether or not the input signal is beingapplied to the timing circuit can be verified in the monitoring circuitby a dual system, involving a signal from the oscillation circuit and adirectly input input signal.

With the present invention the construction may be such that themonitoring circuit monitors for the normalcy of the oscillation circuitbased on a sequential signal change in the various parts of theoscillation circuit for when the oscillation circuit is operatingnormally, and when the oscillation circuit is a PUT oscillation circuitwhich uses a PUT for the switching element, there is provided: aphotocoupler comprising a photodiode and a phototransistor, fordetecting the presence of a gate current of the PUT of the oscillationcircuit; a voltage dividing circuit for dividing a cathode voltage ofthe PUT; a transistor with an emitter side connected to a constantvoltage line and a collector side connected to a collector side of thephototransistor, and a voltage divided by the voltage dividing circuitinput to a base terminal; and a level conversion circuit comprising acapacitor and a diode with the capacitor connected between anintermediate point between the transistor and the phototransistor and acathode side of the diode, and an anode side of the diode connected tothe constant voltage line, and an output signal from the levelconversion circuit is made the output signal from the monitoringcircuit.

With such a construction, a sequential change in the gate current andthe cathode voltage when the oscillation circuit is operating normallycan be verified, and an output signal indicating the normalcy of theoscillation circuit then generated.

With the present invention, the construction may be such that themonitoring circuit monitors for the normalcy of the oscillation circuitbased on a sequential signal change in the various parts of theoscillation circuit for when the oscillation circuit is operatingnormally, and when the oscillation circuit is a PUT oscillation circuitwhich uses a PUT for the switching element, there is provided: a firstphotocoupler comprising a first photodiode and a first phototransistor,for detecting the presence of a gate current of the PUT of theoscillation circuit; a second photocoupler comprising a secondphotodiode and a second phototransistor, for detecting the presence ofan anode current of the PUT of the oscillation circuit; a voltagedividing circuit for dividing a cathode voltage of the PUT; a transistorwith an emitter side connected to a constant voltage line and acollector side connected to a collector side of the secondphototransistor, and a voltage divided by the voltage dividing circuitinput to a base terminal; and a level conversion circuit comprising acapacitor and the first phototransistor with the capacitor connectedbetween an intermediate point between the transistor and the secondphototransistor and an emitter side of the first phototransistor, and acollector side of the first phototransistor connected to the constantvoltage line, and an output signal from the level conversion circuit ismade the output signal from the monitoring circuit.

With such a construction, a sequential change in the gate current, theanode current and the cathode voltage for when the oscillation circuitis operating normally can be verified, and an output signal indicatingthe normalcy of the oscillation circuit then generated.

With the present invention the construction may be such that themonitoring circuit monitors for the normalcy of the oscillation circuitbased on a sequential signal change in the various parts of theoscillation circuit for when the oscillation circuit is operatingnormally, and when the oscillation circuit is a PUT oscillation circuitwhich uses a PUT for the switching element, there is provided: aphotocoupler comprising a photodiode and a phototransistor, fordetecting the presence of a gate current of the PUT of the oscillationcircuit; a voltage dividing circuit for dividing a cathode voltage ofthe PUT; a transistor with an emitter side connected to a constantvoltage line and a collector side connected to a collector side of thephototransistor, and a voltage divided by the voltage dividing circuitinput to a base terminal; and a level conversion circuit comprising acapacitor and a diode with the capacitor connected between anintermediate point between the transistor and the phototransistor and acathode side of the diode, and an anode side of the diode connected tothe input signal line, and an output signal from the level conversioncircuit is made the output signal from the monitoring circuit.

With such a construction, whether or not the input signal is beingapplied to the timing circuit can be verified by a dual system in themonitoring circuit, involving a signal from the oscillation circuit anda directly input input signal.

With the present invention, the construction may be such that themonitoring circuit monitors for the normalcy of the oscillation circuitbased on a sequential signal change in the various parts of theoscillation circuit for when the oscillation circuit is operatingnormally, and when the oscillation circuit is a PUT oscillation circuitwhich uses a PUT for the switching element, there is provided: a firstphotocoupler comprising a first photodiode and a first phototransistor,for detecting the presence of a gate current of the PUT of theoscillation circuit; a second photocoupler comprising a secondphotodiode and a second phototransistor, for detecting the presence ofan anode current of the PUT of the oscillation circuit; a voltagedividing circuit for dividing a cathode voltage of the PUT; a transistorwith an emitter side connected to a constant voltage line and acollector side connected to a collector side of the secondphototransistor, and a voltage divided by the voltage dividing circuitinput to a base terminal; and a level conversion circuit comprising acapacitor and the first phototransistor with the capacitor connectedbetween an intermediate point between the transistor and the secondphototransistor and an emitter side of the first phototransistor, and acollector side of the first phototransistor connected to an input signalline, and an output signal from the level conversion circuit is made theoutput signal from the monitoring circuit.

With the present invention, the construction may be such that themonitoring circuit monitors for the normalcy of the oscillation circuitbased on a sequential signal change in the various parts of theoscillation circuit for when the oscillation circuit is operatingnormally, and when the oscillation circuit is a PUT oscillation circuitwhich uses a PUT for the switching element, there is provided: aphotocoupler comprising a photodiode and a phototransistor, fordetecting the presence of an anode current of the PUT of the oscillationcircuit; and a level conversion circuit comprising a capacitor and thephototransistor of the photocoupler, with one end of the capacitorconnected to an emitter side of the phototransistor which has acollector side connected to an input signal line, and a gate voltageapplied to an other end of the capacitor, and an output signal from thelevel conversion circuit is made the output signal from the monitoringcircuit.

With such a construction, whether or not the input signal is beingapplied to the timing circuit can be verified in the monitoring circuitby a dual system, involving a signal from the oscillation circuit and adirectly input input signal.

With the present invention, the oscillation circuit may be a one shotmulti-vibrator.

With the on-delay circuit according to the present invention, theconstruction incorporates the abovementioned timing circuit of thepresent invention, together with a self hold circuit with the inputsignal for input to the timing circuit input to a first terminal, andthe output signal from the monitoring circuit input to a secondterminal, which produces an output signal when the input signals inputto the first and second terminals are both higher than a power sourcepotential, and which feeds back the output signal to the second terminalto self hold the output signal, and the output signal from the self holdcircuit is made a delay output signal.

With such a construction, only when the timing circuit is normal, is aninput signal which is a higher level than the power source potential,applied to the second terminal of the self hold circuit and an outputsignal thus produced, and this output signal then self held and outputas a delay output signal.

Moreover, with the on-delay circuit according to the present invention,the construction may be such that an input signal line of the timingcircuit and an input signal line to the first terminal of the self holdcircuit are in separate systems, and a resistance is disposed in atleast one of the input signal lines.

With such a construction, in the case of a short circuit fault in anelement connected between the input signal line to the first terminal ofthe self hold circuit and the second terminal, it is possible to preventthe self hold output from being fed back to the second terminal beingapplied to the first terminal. Hence a loss in dependence of theoperation of the self hold circuit on the input signal can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an on-delay circuit of a first embodimentaccording to the present invention;

FIG. 2 is a circuit example of a logical product circuit;

FIG. 3 is an operation time chart for the first embodiment;

FIG. 4 is a circuit diagram of an on-delay circuit of a secondembodiment according to the present invention;

FIG. 5 is a circuit diagram of an on-delay circuit of a third embodimentaccording to the present invention;

FIG. 6 is an operation time chart for the circuit of FIG. 5;

FIG. 7 is a circuit diagram of an on-delay circuit of a fourthembodiment according to the present invention;

FIG. 8 is a circuit diagram of an on-delay circuit of a fifth embodimentaccording to the present invention;

FIG. 9 is an operation time chart for the circuit of FIG. 8;

FIG. 10 is a circuit diagram of an on-delay circuit of a sixthembodiment according to the present invention;

FIG. 11 is a circuit diagram of an on-delay circuit of a seventhembodiment according to the present invention;

FIG. 12 is an operation time chart for the circuit of FIG. 11;

FIG. 13 is a diagram showing signal input conditions for a monitoringcircuit of a timing circuit according to the present invention; (A)being an example for where only a signal from an oscillation circuit isinput, and (B) being an example for where the signal from theoscillation circuit as well as an input signal are input;

FIG. 14 is a circuit diagram of an on-delay circuit of an eighthembodiment according to the present invention;

FIG. 15 is a circuit example of a conventional on-delay circuit; and

FIG. 16 is an operation time chart for the circuit of FIG. 15.

BEST MODE FOR CARRYING OUT THE INVENTION

As follows is a description of embodiments of the present invention,with reference to the drawings.

FIG. 1 shows a circuit of a first embodiment of an on-delay circuitwhich utilizes a timing circuit, according to the present invention.This is a circuit example for where a monitoring circuit is used, whichcarries out monitoring of a PUT oscillation circuit using acharacteristic signal change which is produced only when the PUToscillation circuit is operating normally.

In FIG. 1, the on-delay circuit of this embodiment comprises; a timingcircuit made up of a monitoring circuit 12 and a PUT oscillation circuit11 which uses a PUT as a switching element, as well as a self holdcircuit 13.

The PUT oscillation circuit 11 has the same construction as theconventional circuit shown in FIG. 15, comprising resistors R₁˜R₄, acapacitor C₁, and a PUT, and produces an oscillating output based on theconduction and non conduction of the PUT.

The monitoring circuit 12 comprises: a capacitor C₂ with one endconnected to an intermediate point between a cathode terminal of the PUTof the PUT oscillation circuit 11 and the resistor R₄; a resistor R₅connected to the other end of the capacitor C₂; a photocoupler 20comprising a photodiode PD₁ with an anode side connected to a constantvoltage line L₁ to which a power source potential Vcc is applied, and acathode side connected to the resistor R₅, and a phototransistor PT₁with a collector side connected to the constant voltage line L₁ via aresistor R₆, and an emitter side connected to earth (shown as GND in thefigure); a diode D₁ with a cathode side connected to the constantvoltage line L₁ in parallel with the photodiode PD₁ of the photocoupler20 and an anode side connected to an intermediate point between theresistor R₅ and the cathode side of the photodiode PD₁; a capacitor C₃with one end connected to an intermediate point between the resistor R₆and the phototransistor PT₁; and a diode D₂ with a cathode sideconnected to the other end of the capacitor C₃, and an anode sideconnected to the constant voltage line L₁. Here the capacitor C₂ and theresistor R₅ constitute a differentiating circuit for differentiating thecathode voltage V_(K) of the PUT, while the capacitor C₃ and the diodeD₂ constitute a level conversion circuit for level converting the outputfrom the photocoupler 20.

The self hold circuit 13 has the same construction as the conventionalcircuit shown in FIG. 15, comprising; a logical product circuit 14having two signal input terminals a, b, and a rectifying circuit 15 anda feedback resistor Rf for feeding back an output from the logicalproduct circuit 14 to the second terminal b so that the output is selfheld.

Next is a description of the logical product circuit 14.

The logical product circuit 14 is a two input AND gate with the twoinputs (terminals) each having at least a predetermined lower limitthreshold value (higher than the power source potential Vcc). An outputis only produced when signals of a potential equal to or above therespective lower limit threshold values are input to the two inputterminals. Furthermore, with the fail-safe on-delay circuit there isrequired the characteristic that even with a fault in the logicalproduct circuit, there is no erroneous oscillation, in spite of theinput signals not being applied to the two input terminals.

For this type of logical product circuit, a fail-safe windowcomparator/AND gate can be used. A fail-safe window comparator circuitand its operation are disclosed in Trans. IEE of Japan, Vol. 109-C, No.9 September 1989 under the heading, “A Structural Method for anInterlock System using a Fail-Safe Logic Element having WindowCharacteristics”. Moreover this is also disclosed in literature such asthe Proc. of 19th International Symp. on Multiple-Valued Logic, IEEEComputer Society (May 1989) under the heading of “Application of WindowComparator to Majority Operation”, and the IEEE Transaction onInstrumentation and Measurement, vol. 38, No. 2 (April, 1989) under theheading of “Realization of Fail-Safe Train Wheel Sensor UsingElectromagnetic Induction”. Furthermore, a two input fail-safe windowcomparator implemented by an LSI is disclosed in IEICE Trans. Electron.,vol, E76-C, No. 3, Mar. 1993, pp. 419-427 under the heading of “LSIImplementation and Safety Verification of Window Comparator Used inFail-Safe Multiple-Valued Logic Operation”. The fail-safe windowcomparator circuit has also been previously disclosed in U.S. Pat. No.4,661,880, U.S. Pat. No. 5,027,114 and in Japanese Examined PatentPublication No. 1-23006.

A representative circuit example is shown in FIG. 2, and details of itsoperation are given below.

In FIG. 2, symbols R10, R20 through R170, R180 indicate resistors, Q1through Q7 indicate transistors, A, B indicate input terminals(corresponding to input terminals a, b of the logical product circuit14), Vcc indicates the power source potential for the window comparator,and numeral 203 indicates a rectifying circuit. The parts in FIG. 2outlined by chain lines are direct-coupled direct current amplifyingcircuits 201, 202 which use respective transistors Q1, Q2, Q3, and Q5,Q6, Q7. Moreover, a transistor Q4 constitutes a phase inversion circuit(inverter), and has the function of inverting and amplifying the outputsignal from the direct current amplifying circuit 201. The directcurrent amplifying circuit 201 is connected to the direct currentamplifying circuit 202 by way of the transistor Q4, and the output fromthe direct current amplifying circuit 202 is direct-coupled to thedirect current amplifying circuit 201 by way of the resistor R180, thusmaking up a feedback oscillation circuit.

Conditions for oscillation of the circuit of FIG. 2 are determined bythe following equations, where V10 is the input potential of the inputterminal A, and V20 is the input potential of the input terminal B;

For the input terminal A

(r₁₀+r₂₀+r₃₀)Vcc/r₃₀<V₁₀<(r₆₀+r₇₀)Vcc/r₇₀  (1)

For the input terminal B,

(r₁₁₀+r₁₂₀+r₁₃₀)Vcc/r₁₃₀<V₂₀<(r₁₆₀+r₁₇₀)Vcc/r₁₇₀  (2)

In the above two equations, r₁₀ through r₁₇₀ indicate the resistancevalues of the respective resistors. Moreover, symbol < means less thanor approximately equal. In equation (1) (r₁₀+r₂₀+r₃₀)Vcc/r₃₀ representsthe approximate lower limit threshold value of the input terminal A,while (r₆₀+r₇₀)Vcc/r₇₀ represents the approximate upper limit thresholdvalue of the input terminal A. In a similar manner,(r₁₁₀+r₁₂₀+r₁₃₀)Vcc/r₁₃₀ in equation (2) represents the approximatelower limit threshold value of the input terminal B, while(r₁₆₀+r₁₇₀)Vcc/r₁₇₀ represents the approximate upper limit thresholdvalue of the input terminal B. When the input terminal A has an inputlevel V10 within a range satisfying equation (1), and the input terminalB has an input level V20 within a range satisfying equation (2), thecircuit of FIG. 2 oscillates and an alternating current output signal isproduced at a terminal Uf. This alternating current output signal isrectified in the rectifying circuit 203 to become a direct currentoutput signal.

The oscillation process in the circuit of FIG. 2 occurs when the voltagelevels of the input signals to the input terminals A and B both satisfyequations (1) and (2), and the transistors Q1 to Q7 are switched forexample as follows:Q6:OFF→Q7:OFF→Q1:ON→Q2:ON→Q3:ON→Q4:OFF→Q5:ON→Q6:ON→Q7:ON→Q1:OFF→Q2:OFF→Q3:OFF→Q4:ON→Q5:OFF→Q6:OFF→and so on.

The circuit of FIG. 2, has the characteristic that even if a shortcircuit or disconnection fault occurs in the transistors and resistorswhich make up the circuit; “there is no situation wherein oscillationerroneously occurs even in spite of the input voltages determined byequations (1) and (2) not being supplied to the two input terminals Aand B”. For example, it has the characteristic that if any one of thetransistors Qi (i=1˜7) is faulty, then the phase of the feedback loop isinverted so that a feedback oscillation cannot be produced. Moreover,insofar as an input voltage at the respective input terminals A and Bwhich is higher than the power source potential Vcc, is not supplied tothe collector side of the transistors Q1, Q3, Q4 and the transistors Q5,Q7, then switching signals cannot be output to the bases of thetransistors succeeding these transistors, and oscillation is thus notpossible.

The rectifying circuit 203 of FIG. 2 rectifies the AC output signalproduced due to oscillation of the direct current amplifying circuit202, to give a direct current output signal. The method of rectifyingthe oscillating output signal to give a direct current output signalincludes both the case where the output signal from the oscillationcircuit of FIG. 2 is amplified before inputting to the rectifyingcircuit, and the case where this is input to the rectifying circuit viaa transformer. Moreover, in FIG. 2, a phase inversion amplifying circuitcomprising the transistor Q4 is inserted as an inverter between, butseparate from, the two direct current amplifying circuits 201, 202. Thisphase inversion amplifying circuit may however be incorporated into oneof the two direct current amplifying circuits.

With this embodiment, the self hold circuit 13 is constructed such thatthe AC signal from the terminal Uf shown in FIG. 2 of the logicalproduct circuit 14, is input to the rectifying circuit 15 and rectified,and then input to the second terminal b via the feedback resistor Rf.Furthermore, the output from the rectifying circuit 203 becomes thedelay output signal from the self hold circuit 13.

With the monitoring circuit 12 of the present embodiment, the normalcyof the PUT oscillation circuit 11 is verified by monitoring the cathodeterminal voltage V_(K) of the PUT oscillation circuit 11.

That is to say, as shown by the operation time chart (refer to FIG. 16)of the conventional circuit of FIG. 15, the PUT cathode terminal voltageV_(K) of the PUT oscillation circuit rises steeply at a time τ₁ fromafter applying the input signal V_(IN), and then falls steeply at a timeτ₂. If a fault occurs in the PUT oscillation circuit, the steep drop asis seen at the time τ₂ does not occur in the cathode terminal voltageV_(K). For example, if a short circuit fault occurs between the gateterminal and the cathode terminal of the PUT during timing afterapplying the input signal V_(IN), then the cathode terminal voltageV_(K) will only rise and will not fall. Also, if the input signal V_(IN)is applied in a condition with a short circuit fault occurring betweenthe gate terminal and the cathode terminal, the same happens.Furthermore, also if a short circuit fault occurs between the anodeterminal, the gate terminal and the cathode terminal of the PUT duringtiming, there will be no steep drop of the cathode terminal voltageV_(K). Consequently if the construction is such that the cathodeterminal voltage V_(K) is input to the monitoring circuit 12, and anoutput signal is only output to the self hold circuit 13 when verifiedthat there has been a steep drop in the cathode terminal voltage V_(K),then a fail-safe on-delay circuit can be realized.

Next is a description of the operation of the on-delay circuit of thefirst embodiment, with reference to the operation time chart of FIG. 3.In the description, the application of the input signal V_(IN) isindicated by the voltage level of the input signal V_(IN) becoming equalto or above a lower limit threshold value V_(L1) held by the firstterminal a of the logical product circuit 14, while the cancelling ofthe input signal V_(IN) is indicated by the voltage level of the inputsignal V_(IN) becoming less than the lower limit threshold value held bythe first terminal a of the logical product circuit 14. The operation ofthe PUT oscillation circuit 11 is the same as for the PUT oscillationcircuit 1 of the conventional circuit shown in FIG. 15, and hencedescription is omitted.

With the monitoring circuit 12, the PUT cathode terminal voltage V_(K)is differentiated by the capacitor C₂ and the resistor R₅ and convertedto a current i_(C2). The current i_(C2) is a positive value when flowingin the direction indicated by the arrow in FIG. 1. As shown in FIG. 3,due to the rising of the cathode terminal voltage V_(K) when the PUToscillation circuit 11 changes from condition A to condition B, apositive pulse current flows as the current i_(C2), while due to thefalling of the cathode terminal voltage V_(K) when changing fromcondition B to condition A, a negative pulse current flows as thecurrent i_(C2). In the case where the input signal V_(IN) is not applied(condition C), or when applied but timing is being carried out(condition A), then the cathode terminal voltage V_(K) keeps a constantvalue and does not change, and hence the current i_(C2) is zero.

When the negative pulse current is produced when changing from conditionB to condition A, this negative current i_(C2) flows via the photodiodePD₁, causing the phototransistor PT₁ to come on. The impedance of thephototransistor PT₁ at this time is set so as to become less than theresistance of the resistor R₆. Therefore, the collector terminal voltageof the phototransistor PT₁ drops to become approximately GND level.Furthermore, since the cathode terminal voltage of the diode D₂ isapproximately the power source potential Vcc, then the capacitor C₃ ischarged via the diode D₂ and the phototransistor PT₁, to the powersource potential Vcc. When the differential operation is completed andthe current flowing in the photodiode PD₁ ceases, the phototransistorPT₁ goes off resulting in a higher impedance than the resistance of theresistor R₆. Therefore the collector terminal voltage of thephototransistor PT₁ rises and becomes approximately the power sourcepotential Vcc. This change in the collector terminal voltage of thephototransistor PT₁ is level converted by the capacitor C₃ so that apulse voltage signal of approximately two times the frequency of thepower source potential Vcc is produced as the output signal Vo. Thispulse voltage Vo which has a level equal to or greater than a lowerlimit threshold value V_(L2) of the second terminal b of the logicalproduct circuit 14, is then input to the second terminal b of thelogical product circuit 14.

When the pulse voltage Vo is input to the second terminal b under thecondition that the input signal V_(IN) is being applied to the firstterminal a of the logical product circuit 14, then the logical productcircuit 14 generates an output signal Z (delay output signal of theon-delay circuit). That is to say, the delay output signal Z of theon-delay circuit is produced after the elapse of time τ₂ (=τ₁+τ′) fromafter input of the input signal V_(IN) to the PUT oscillation circuit11. The AC signal from the logical product circuit 14 is rectified bythe rectifying circuit 15 simultaneously with the generation of theoutput signal Z, and then fed back via the feedback resistor Rf to thesecond terminal b of the logical product circuit 14. Due to the input ofthis feedback signal to the second terminal b, the output signal Zcontinues to be produced while the input signal V_(IN) is being appliedto the first terminal a, even after the pulse voltage Vo is cancelled.If the input signal V_(IN) is cancelled, the output signal Z as well asthe feedback signal are simultaneously cancelled.

If a fault occurs in the PUT oscillation circuit 11, there will be nosteep drop in the cathode terminal voltage V_(K) of the PUT. Ifappropriate values are selected for the capacitor C₂ and the resistorR₅, so that in the case where the cathode terminal voltage V_(K) doesnot drop steeply, the current flowing in the photodiode PD₁ is madesufficiently small and the impedance of the phototransistor PT₁ is kepthigher than the resistance of the resistor R₆, then the collectorterminal voltage of phototransistor PT₁ will not change and will be keptat approximately the power source potential Vcc. Hence the capacitor C₃will not be noticeably charged, and an output signal Vo of a level equalto or above the lower limit threshold value V_(L2) of the secondterminal b of the logical product circuit 14 will not be produced.

Also if a fault occurs in the monitoring circuit 12, an erroneous outputwill not be produced. For example if a disconnection fault occurs in thecapacitor C₂ or the resistor R₅ or the photodiode PD₁, the signal willnot be transmitted and the phototransistor PT₁ will thus become acontinuous high impedance. Hence an erroneous output will not beproduced. Furthermore, if a short circuit fault occurs in the capacitorC₂, since the cathode terminal voltage V_(K) is always equal to or abovethe power source potential Vcc, a current will not flow in thephotodiode PD₁, and the phototransistor PT₁ will thus become a highimpedance. Hence an erroneous output will not be produced.

Utilizing the fact that the input and output of the monitoring circuit12 are insulated from each other by the photocoupler 20, then it ispossible to have a monitoring circuit 12′ instead as shown in FIG. 4,made up of the circuit which comprises the resistor R₆, thephototransistor PT₁, the capacitor C₃ and the diode D₂, inserted betweenthe power source and GND, and is inserted between an input line L₂ forthe input signal V_(IN) and the fixed voltage line L₁.

In the case of the construction of the monitoring circuit 12′ of FIG. 4which illustrates a second embodiment of the present invention, a pulsevoltage signal Vo′ produced following the voltage change in thecollector terminal side of the phototransistor PT₁, is superimposed onthe input signal V_(IN) as shown in the operation time chart of FIG. 3.Therefore, by verifying the voltage level of the pulse voltage signalVo′, verification of the timing operation, and that the input signalV_(IN) is being applied, can be carried out simultaneously (dualsystem). There is thus the advantage that the fail-safe characteristicsare improved. Needless to say, with the circuit configuration of FIG. 4,there is the proviso that a lower limit threshold value V_(L2)′ of thesecond terminal b of the logical product circuit 14 must be set to ahigher value than the lower limit threshold value V_(L2) for FIG. 1.

Now, instead of the diode D₁ used in the circuit of FIG. 1 and FIG. 4, aresistor may be used.

Next is a description of a circuit example which uses a monitoringcircuit which carries out monitoring of the PUT oscillation circuitbased on a sequential signal change for when the PUT oscillation circuitis operating normally.

At first is a description concerning the structural theory of a relevantmonitoring method.

The number of input signals required for the monitoring circuit tomonitor for the operation normalcy of the PUT oscillation circuit in thecase where the fact the PUT is oscillating normally (that is to saychanges from condition A to condition B and then back to condition A) isverified using the sequential changes in the voltage or the currentcondition of the various part of the circuit, is explained below usingthe conventional basic PUT oscillation circuit shown in FIG. 15.

The currents in the PUT oscillation circuit are the anode current i_(A),the gate current i_(G), the cathode current i_(K), the bias currenti_(B1), and the bias current i_(B2). The charging current flowingthrough the resistor R₁ is normally smaller than the other currents andhence is not considered here. The voltages are the anode voltage V_(A),the cathode voltage V_(K), and the gate voltage V_(G).

All of these five currents and three voltages can be input to themonitoring circuit, and verification of the normalcy of the PUToscillation circuit carried out from their sequential changes. Howeverin this case, the number of input signals becomes large and the circuitcomplicated and hence this is not really practical.

The relationships obtained between the five currents and three voltagesare given by the following six equations:

i _(A) +i _(G) =i _(K)

i _(G) +i _(B2) =i _(B1)

i _(G) ≈i _(B1)(PUT:ON), i _(G)=0(PUT:OFF)

V_(K)=R₄ *i _(K)

V_(G)=R₃ *i _(B2)

C₁*dV_(A)/dt≈−i _(A)

For these six equations there are two independent variables out of thefive currents and the three voltage (i.e. the total of eight variables).That is to say, if two variables of the five currents and the threevoltages are known, then the remaining six variables can be ascertainedfrom the above six equations.

Consequently, in order to verify the operation of the PUT oscillationcircuit, it is sufficient to input at least two or more variables of thefive currents and the three voltages to the monitoring circuit.

FIG. 5 shows a circuit diagram of a third embodiment of an on-delaycircuit. This is a circuit example for where a monitoring circuit isused which monitors using the gate current i_(G) and the cathode voltageV_(K). Parts the same as for the first embodiment are indicated by thesame symbols and description is omitted.

In FIG. 5, a monitoring circuit 30 comprises: resistors R₇, R₈ forvoltage dividing the cathode terminal voltage V_(K) of a PUT; atransistor Tr₁ with an emitter terminal connected to a constant voltageline L₁ and a collector terminal connected to a collector terminal of aphototransistor PT₃₁ of a photocoupler 31 to be described later, and avoltage divided by the beforementioned resistors R₇, R₈ applied to abase terminal; a photocoupler 31 comprising a photodiode PD₃₁ disposedbetween a gate terminal of the PUT and an intermediate point betweenresistors R₂ and R₃, and the beforementioned phototransistor PT₃₁; acapacitor C₄ with one end connected to an intermediate point between thetransistor Tr₁ and the phototransistor PT₃₁; and a diode D₃ with acathode terminal connected to the other end of the capacitor C₄ and ananode terminal connected to the constant voltage line L₁. Here theresistors R₇, R₈ constitute a voltage dividing circuit, while thecapacitor C₄ and the diode D₃ constitute a level conversion circuit.

Next is a description of the operation, with reference to the operationtime chart shown in FIG. 6.

The gate current i_(G) is input to the monitoring circuit 30 using thephotocoupler 31. Furthermore, the cathode terminal voltage V_(K) isinput as is to the monitoring circuit 30, and then voltage divided bythe resistors R₇ and R₈ inside the monitoring circuit 30, and input to abase terminal of the transistor Tr₁.

When the input signal V_(IN) is applied, the PUT oscillation circuit 11becomes condition A and the PUT goes off. The gate current i_(G) is thuszero and hence the phototransistor PT₃₁ is off, giving a high impedance.Moreover, since the cathode current i_(k) of the PUT also does not flow,then a base terminal voltage Vα of the transistor Tr₁ falls to a levelwhere the transistor Tr₁ comes on. At this time, a collector terminalvoltage Vβ of the transistor Tr₁ is approximately at the power sourcepotential Vcc, and the cathode terminal voltage of the diode D₃ is alsoapproximately at the power source potential Vcc. Consequently thecapacitor C₄ is in the nearly discharged condition.

With condition B of the PUT oscillation circuit 11, the PUT is on sothat the charge stored in the capacitor C1 passes from the anodeterminal to the cathode terminal of the PUT, and then passes through theresistor R₇ and the resistor R₈ to thus discharge. Due to the currentflowing through the resistor R₇ and the resistor R₈, the base terminalvoltage Va of the transistor Tr₁ increases to a level where thetransistor Tr₁ goes off. Moreover, since the gate current i_(G) flows,then the phototransistor PT₃₁ comes on so that the impedance drops.Consequently, the collector terminal voltage Vβ of the transistor Tr₁drops to become approximately GND level. Since the cathode terminalvoltage of the diode D₃ is approximately the power source potential Vcc,then the capacitor C₄ is charged to the power source potential Vcc viathe diode D₃ and the phototransistor PT₃₁.

Then when the PUT oscillation circuit 11 again becomes condition A, thePUT goes off. The gate current i_(G) thus becomes zero so that thephototransistor PT₃₁ goes off, giving a high impedance. Since thecathode current i_(k) ceases to flow, then the base terminal voltage Vαof the transistor Tr₁ falls to a level where the transistor Tr₁ comeson. The collector terminal voltage Vβ of the transistor Tr₁ then risesto become approximately the power source potential Vcc. The change inthe collector terminal voltage Vβ is level converted by the capacitorC₄, and a pulse voltage signal is input to the second terminal b of thelogical product circuit 14 as the output Vo. The delay output signal Zthus continues to be produced from this point in time until the inputsignal V_(IN) is cancelled.

The on-delay circuit shown in FIG. 5 does not produce an erroneousoutput at the time of a fault in the PUT oscillation circuit.

For example, if a short circuit fault occurs between the gate terminaland the cathode terminal of the PUT, then a current flows in thephotodiode PD₃₁ so that the impedance of the phototransistor PT₃₁ drops.However, the current passed by the photodiode PD₃₁ flows as is throughthe resistor R₇ and the resistor R₈. The resistances of the resistorsR₂, R₃, R₇ and R₈ can thus be set to an appropriate value so that thetransistor Tr₁ goes off due to this current. If this is done, then atthe time of the abovementioned fault, the collector terminal voltage Vβof the transistor Tr₁ will be fixed at approximately GND level and thuswill not change, and hence an erroneous pulse voltage will not beproduced as the output Vo. Moreover, also if a short circuit faultoccurs between the anode terminal and the gate terminal and the cathodeterminal of the PUT, then for the same reason, an erroneous output willnot be produced.

Furthermore, also if a fault occurs in the monitoring circuit 30, anerroneous output will not be produced. For example, if a disconnectionfault occurs in the resistor R₇, the transistor Tr₁ will remain on.Therefore, the collector terminal voltage Vβ will be fixed atapproximately the power source potential Vcc, and hence an erroneousoutput will not be produced. If a disconnection fault occurs in theresistor R₈, the transistor Tr₁ will remain off. Therefore, thecollector terminal voltage Vβ will not be able to rise to the powersource potential Vcc and hence an erroneous output will not be produced.The same also applies if a short circuit fault occurs in the baseterminal, the collector terminal, or the emitter terminal of thetransistor Tr₁. If a disconnection fault occurs in the collectorterminal or the emitter terminal of the phototransistor PT₃₁, then thecapacitor C₄ cannot be charged and hence an erroneous output will not beproduced. Moreover, if a short circuit fault occurs in the capacitor C₄,the output Vo to the second terminal b of the logical product circuit 14will become equal to or less than the power source potential Vcc, andhence an erroneous output will not be produced.

The circuit configuration of a fourth embodiment of the presentinvention is shown in FIG. 7 for the case where the anode terminal ofthe diode D₃ is connected to the input signal line L₂.

The operation of the PUT oscillation circuit 11 and a monitoring circuit30′ is the same as for the circuit shown in FIG. 5. Aspects of theoutput Vo′ are shown in FIG. 6. Since the pulse voltage signal issuperimposed on the input signal V_(IN) and then output, then this hasthe advantage that by monitoring the level of the output Vo′,verification of the timing operation, and that the input signal V_(IN)is being applied, can be carried out simultaneously. Needless to say,with the circuit configuration of FIG. 7, there is the proviso that thelower limit threshold value V_(L2)′ of the second terminal b of thelogical product circuit 14 must be set to a higher value than the lowerlimit threshold value V_(L2) for FIG. 5.

Now, the diode D₃ in the circuits shown in FIG. 5 and FIG. 7 may bereplaced with a resistor. Moreover, the diode D₃ may be replaced by aresistor and the location of this and that of the phototransistor PT₃₁interchanged. The resistors R₄ and R₉ shown by dotted lines in FIG. 5and FIG. 7, may be respectively inserted for example for stabilising thePUT terminal potential.

The case will now be considered with the PUT oscillation circuit 11 ofthe on-delay circuit shown in FIG. 5 or FIG. 7, for where a shortcircuit fault occurs between the gate terminal and the anode terminal ofthe PUT, when the capacitor C₁ has practically no charge immediatelyafter applying the input signal V_(IN).

At this time, the charge current flowing to the capacitor C₁ via theresistor R₂ and the photodiode PD₃₁ is at first large and then falls tozero as the capacitor C₁ becomes charged. While the current is flowingin the photodiode PD₃₁, the phototransistor PT₃₁ is on, giving a lowimpedance. Moreover, the transistor Tr₁ remains on during this time. Ifthe impedance when the transistor Tr₁ is on is lower than the impedanceof the phototransistor PT₃₁ during this time, the collector terminalvoltage Vβ of the transistor Tr₁ will remain at the approximate powersource potential Vcc. Therefore the capacitor C₄ will not be charged,and hence an erroneous output signal will not be produced. In order toachieve this, then normally a high field effect type transistor isselected for the transistor Tr₁.

However, in the case where the impedance relationships are opposite,then during the time that the impedance of the phototransistor PT₃₁ islower than the impedance for when the transistor Tr₁ is on, thecollector terminal voltage Vβ of the transistor Tr₁ drops to becomeapproximately GND level and the capacitor C₄ is charged. If after this,the impedance for when the transistor Tr₁ is on becomes lower than theimpedance of the phototransistor PT₃₁, then the collector terminalvoltage Vβ of the transistor Tr₁ will rise to become approximately thepower source potential Vcc, and hence an erroneous output will occur.

As a means for preventing this situation, a method wherein the number ofinputs to the monitoring circuit is increased (giving redundantinformation) can be considered. Circuit configuration examples for caseswith this redundancy are given below. FIG. 8 shows a circuit example forthe case where this redundancy is provided in a fifth embodiment of theon-delay circuit. This is a circuit example for where a monitoringcircuit is used which monitors using the gate current i_(G), the anodecurrent i_(A), and the cathode voltage V_(K). Parts the same as for thefirst embodiment are indicated by the same symbols and description isomitted.

In FIG. 8, a photocoupler is added to the on-delay circuit shown in FIG.5, for further monitoring the anode current i_(A).

That is to say, a photodiode PD₄₁ of a second photocoupler 41 isprovided between an intermediate point between the resistor R₁ and thecapacitor C₁, and the anode terminal of the PUT, while a phototransistorPT₄₁ of the second photocoupler 41 is connected between the collectorterminal side of the transistor Tr₁ and earth. Furthermore, aphototransistor PT₃₁ of the first photocoupler 31 is inserted instead ofthe diode D₃, between the capacitor C₄ and the constant voltage line L₁.

With such a construction, if as mentioned above a short circuit faultoccurs between the gate terminal and the anode terminal of the PUT, thenthe charging current flowing to the capacitor C₁ via the resistor R₂ andthe photodiode PD₃₁ is stopped by the photodiode PD₄₁ of the secondphotocoupler 41 and hence does not flow. If this did flow, with thephotodiode PD₄₁ at that time becoming short circuited, then thephototransistor PT₄₁ would not become a low impedance. Therefore thecollector terminal voltage Vβ of the transistor Tr₁ would remainapproximately at the power source potential Vcc without change, andhence the capacitor C₄ would not be charged. Hence an erroneous outputwould not be produced.

Basically the operation is the same as for the on-delay circuit of FIG.5, and hence description of the operation is omitted. Needless to say,the circuit of FIG. 8 satisfies the safety conditions of the on-delaycircuit of FIG. 5. An operation time chart for the circuit of FIG. 8 isshown in FIG. 9.

As a sixth embodiment, then as shown in FIG. 10, it is also possible tohave the collector terminal of the phototransistor PT₃₁ connected to theinput signal line L₂. Aspects of the output Vo′ for this case are shownas Vo′ in the operation chart of FIG. 9.

With such a construction, verification of the timing operation, and thatthe input signal V_(IN) is being applied, can be carried outsimultaneously, with the advantage that the fail-safe characteristicsare improved. Needless to say, with the circuit configuration of FIG.10, there is the proviso that the lower limit threshold value V_(L2)′ ofthe second terminal b of the logical product circuit 14 must be set to ahigher value than the lower limit threshold value V_(L2) for FIG. 8.

Now, the locations of the phototransistor PT₃₁ and the phototransistorPT₄₁ in the circuits shown in FIG. 8[and FIG. 10 may be interchanged.Moreover, the resistors R₄, R₉, and R₁₁ shown by dotted lines in FIG. 8and FIG. 10, may be respectively inserted for example for stabilisingthe PUT terminal potential.

FIG. 11 shows a circuit diagram of a seventh embodiment of an on-delaycircuit. This is a circuit example for where a monitoring circuit isused which monitors using the anode current i_(A) and the gate voltageV_(G).

In FIG. 11, a monitoring circuit 50 comprises: a capacitor C₅ with oneend connected to an intermediate point between a resistor R₂ and aresistor R₃; and a photocoupler 51 comprising a photodiode PD₅₁ providedbetween an intermediate point between a resistor R₁ and a capacitor C₁,and an anode terminal of a PUT, and a phototransistor PT₅₁ with anemitter terminal connected to the other end of the capacitor C₅ and acollector terminal connected to an input signal line L₂.

The operation of the above circuit will now be described with referenceto the operation time chart shown in FIG. 12.

When an input signal V_(IN) is applied, a PUT oscillation circuit 11becomes condition A. At this time the PUT is off and the anode currenti_(A) is zero. Furthermore, the gate current i_(G) is also zero, and thegate voltage V_(G) becomes a value for the input signal V_(IN), voltagedivided by the resistor R₂ and the resistor R₃ (hereunder this voltageis referred to as V_(Ga)).

When the PUT oscillation circuit 11 changes from condition A tocondition B, the PUT comes on and the anode current i_(A) and the gatecurrent i_(G) flow. Due to the anode current i_(A) flowing through thephotodiode PD₅₁, the phototransistor PT₅₁ becomes a low impedance sothat the emitter terminal voltage of the phototransistor PT₅₁ rises tobecome approximately the input signal V_(IN). Moreover, since themajority of the current flowing through the resistor R₂ flows as thegate current i_(G), then the gate voltage V_(G) drops to becomeapproximately the power source potential Vcc. Consequently, thecapacitor C₅ is charged to a voltage of approximately V_(IN)−Vcc.

Next, when the PUT oscillation circuit 11 changes from condition B tocondition A, the PUT goes off so that the anode current i_(A) becomeszero, and the phototransistor PT₅₁ becomes a high impedance. The gatevoltage V_(G) thus rises from the power source potential Vcc to againbecome V_(Ga). The change in voltage of the gate voltage V_(G) is levelconverted by the capacitor C₅, so that a high wave pulse voltage(V_(IN)+V_(Ga)−Vcc) is produced as the output Vo. This pulse voltage isinput as a trigger signal to a second terminal b of a logical productcircuit 14, and the logical product circuit 14 then produces a delayoutput signal Z. After this, the delay output signal Z continues to beproduced while the input signal V_(IN) is being applied, and if theinput signal V_(IN) is cancelled, the delay output signal Z also stops.

With this circuit configuration also, an erroneous output will not beproduced due to a fault in the PUT oscillation circuit 11 or a fault inthe monitoring circuit 50. For example, if a short circuit fault occursbetween the gate terminal and the cathode terminal of the PUT, the gatevoltage V_(G) becomes fixed at the power source potential Vcc so thatthe rising change in V_(Ga) necessary for the pulse voltage outputcannot be effected. Hence an erroneous output will not be produced.Moreover, also if a short circuit fault occurs between the anodeterminal and the gate terminal and the cathode terminal of the PUT,since the gate voltage V_(G) is fixed at the power source potential Vcc,then similarly an erroneous output will not be produced. Furthermore, ifa short circuit fault occurs in the phototransistor PT₅₁ of themonitoring circuit 50, the output Vo will be fixed at the input signalV_(IN). Therefore a pulse voltage superimposed on the input signalV_(IN) will not be output as the output Vo.

The resistor R₁₁ shown by the dotted line in FIG. 11, may be insertedfor example for stabilizing the PUT terminal potential.

From the beforementioned respective embodiments, then with the timingcircuit comprising the oscillation circuit and the monitoring circuit,the cases as shown in FIG. 13 can be considered where, for the signalinput condition to the monitoring circuit, then as shown in FIG. 13 (A),only the signal information from the oscillation circuit is received(corresponding to the embodiments of FIG. 1, FIG. 5 and FIG. 8), and, asshown in FIG. 13 (B), in addition to the signal information from theoscillation circuit, the input signal for input to the oscillationcircuit is also directly received (corresponding to the embodiments ofFIG. 4, FIG. 7, FIG. 10 and FIG. 11).

In the case of the construction of FIG. 13 (B), the application of theinput signal V_(IN) to the timing circuit can be verified by a dualsystem, from the output from the oscillation circuit, and from the inputsignal input directly to the monitoring circuit. Hence the fail-safecharacteristic can be further increased, and the reliability of thetiming circuit improved.

It can be considered that in the case where, in the circuit of FIG. 4, ashort circuit fault occurs in the diode D₂, or in the circuit of FIG. 7,a short circuit fault occurs in the diode D₃, or in the circuit of FIG.11, a short circuit fault occurs in the phototransistor PT₅₁, then thefeedback input to the second terminal b of the logical product circuit14 will also be applied to the first terminal a. Therefore, theoperation of the logical product circuit 14 will lose its dependency onthe input signal V_(IN). In order to avoid this situation, the signalinput line to the PUT oscillation circuit 11 and the signal input lineto the first terminal a can be in separate systems, so that as a resultfor example of a short circuit fault, the feedback input will not beinput to the first terminal a.

As a method of having the signal input line to the logical productcircuit 14 and the signal input line to the PUT oscillation circuit inseparate systems, then for example in the case where the input signalV_(IN) is an output from an AC-DC conversion circuit (for example arectifying circuit or the like, and possibly including an amplifyingcircuit and a transformer coupling circuit or the like), a circuitconfiguration of an eighth embodiment of the present invention as shownin FIG. 14 can be considered.

In FIG. 14, an input signal to a first terminal a of a logical productcircuit 14 is made V_(IN1), while an input signal to a PUT oscillationcircuit 11 and for example a monitoring circuit 12′ is made V_(IN2). Thetwo input signals V_(IN1), V_(IN2) are signals for where a common ACsignal V_(AC) has been converted to DC. With the input signal V_(IN1),the AC signal V_(AC) is converted to DC by a first AC-DC conversioncircuit 61 via a resistor R_(i1), and then applied to the first terminala of the logical product circuit 14 by means of a first input signalline L₂₁. With the input signal V_(IN2), the AC signal V_(AC) isconverted to DC by a second AC-DC conversion circuit 62 via a resistorR_(i2), and then applied to the PUT oscillation circuit 11 and themonitoring circuit 12′ by means of a second input signal line L₂₂.

With this circuit configuration, the worst fault where the feedbacksignal to the second terminal b of the logical product circuit 14 isinput to the first terminal a of the logical product circuit 14, is forwhere a short circuit fault occurs between the respective input andoutput terminals of the first AC-DC conversion circuit 61 and the secondAC-DC conversion circuit 62. In practice, the occurrence of such a faultunlikely. However with such a fault, the feedback signal to the secondterminal b is input to the first terminal a via at least the resistorR_(i1) and the resistor R_(i2).

Consequently the resistances can be determined so that by resistivedividing the resistances of the added resistance value of the resistorR_(i1) and the resistor R_(i2) (R_(i1)+R_(i2)) and the input impedanceof the first terminal a of the logical product circuit 14, the level ofthe feedback signal for input to the first terminal a becomes less thanthe lower limit threshold value held by the first terminal a. If this isdone, then the logical product circuit 14 will not oscillate erroneouslywith only the feedback signal being input to the first terminal a as aresult of the feedback signal to the second terminal b of the logicalproduct circuit 14 being transmitted to the input signal line L₂₂ due toa fault in the monitoring circuit 12′. Hence the situation where theoperation of the logical product circuit 14 loses its dependency on theinput signal V_(IN1) (in fact the AC signal Vac) can be prevented.

With the circuit configuration of FIG. 14, the resistors R_(i1) andR_(i2) are inserted on the respective input sides of the first andsecond AC-DC conversion circuits 61, 62. However it is sufficient tohave just one resistor corresponding to the beforementioned resistancevalue R_(i1)+R_(i2), in only one input side.

With the respective embodiments of the present invention, the exampleshave been given for a PUT oscillation circuit which uses a PUT in theoscillation circuit. However it will be clear that instead of a PUT, anoscillation circuit which uses a UJT (uni junction transistor) or adouble base diode can be used. For the oscillation circuit, a circuitwhich carries out a relaxation oscillation operation can be used. Forexample a one shot multi-vibrator can be used. Moreover, in thedetection of the current in the timing circuit, the description involvesusing a photocoupler. However as well as such a contactless relay, arelay having contact points, such as an electromagnetic relay can beused. Furthermore, with the configuration examples of the monitoringcircuits, the descriptions were for where the transistor was a bipolartransistor. However other types of switching element (for example aMOSFET) can be used.

With the present invention as described above, the construction involvesproviding a monitoring circuit for monitoring for the normalcy of theoscillation circuit, to thus verify if the oscillation circuit isnormal. Therefore even if there is a fault in the oscillation circuit orthe monitoring circuit, the generation of an erroneous timing output canbe prevented, and the timing circuit thus made fail-safe.

Furthermore, by inputting both the output signal from the oscillationcircuit and the input signal, to the monitoring circuit, then the factthat the input signal has been applied to the timing circuit can beverified by a dual system[?], and hence the fail-safe characteristicscan be further improved.

Moreover, if the oscillation circuit and the monitoring circuitmalfunction, it is possible to prevent the generation of an erroneousdelay output signal. Hence the fail-safe characteristics of the on-delaycircuit can be increased. Furthermore, it is possible to prevent thefeedback signal to the second terminal of the self hold circuit frombeing applied to the first terminal due to a fault in the circuitelements. Hence the fail-safe characteristics of the on-delay circuitcan be further improved.

INDUSTRIAL APPLICABILITY

The present invention enables improvement in the fail-safecharacteristics of control mechanisms and the like which use timingcircuits or on-delay circuits. Hence industrial applicability isconsiderable.

We claim:
 1. A fail-safe timing circuit characterized in comprising: anoscillation circuit which produces an oscillating output using theswitching of a switching element, after the lapse of a previously setpredetermined time from after applying an input signal; and a monitoringcircuit for monitoring for the normalcy of said oscillation circuitbased on electrical operating conditions of said oscillation circuit,and generating an output signal only when said oscillation circuit isnormal; wherein with said monitoring circuit, a signal from saidoscillation circuit, and said input signal are input thereto.
 2. Afail-safe timing circuit according to claim 1, wherein said monitoringcircuit monitors for the normalcy of said oscillation circuit based on asignal change which is produced only when said oscillation circuit isoperating normally.
 3. A fail-safe timing circuit characterized incomprising: an oscillation circuit which produces an oscillating ouputusing the switching of a switching element, after the lapse of apreviously set predetermined time from after applying an input signal;and a monitoring circuit for monitoring for the normalcy of saidoscillation circuit based on electrical operating conditions of saidoscillation circuit, and generating an output signal only when saidoscillation circuit is normal; wherein said monitoring circuit monitorsfor the normalcy of said oscillation circuit based on a sequentialsignal change in the various parts of said oscillation circuit for whensaid oscillation circuit is operating normally.
 4. A fail-safe timingcircuit characterized in comprising: an oscillation circuit whichproduces an oscillating ouput using the switching of a switchingelement, after the lapse of a previously set predetermined time fromafter applying an input signal; and a monitoring circuit for monitoringfor the normalcy of said oscillation circuit based on electricaloperating conditions of said oscillation circuit, and generating anoutput signal only when said oscillation circuit is normal; wherein saidmonitoring circuit monitors for the normalcy of said oscillation circuitbased on a signal change which is produced only when said oscillationcircuit is operating normally, and when said oscillation circuit is aPUT oscillation circuit which uses a PUT (programmable uni junctiontransistor) for the switching element, there is provided: adifferentiating circuit for differentiating a cathode terminal voltageof said PUT; a photocoupler comprising a photodiode with an anode sideconnected to a constant voltage line and a cathode side connected to anoutput terminal of said differentiating circuit, and a phototransistorwith a collector side connected to the constant voltage line via aresistor, and an emitter side connected to earth; and a level conversioncircuit comprising a capacitor and a diode with said capacitor connectedbetween an intermediate point between said resistor and saidphototransistor and a cathode side of said diode, and an anode side ofsaid diode connected to said constant voltage line, and an output signalfrom said level conversion circuit is made the output signal from saidmonitoring circuit.
 5. A fail-safe timing circuit according to claim 1,wherein said monitoring circuit monitors for the normalcy of saidoscillation circuit based on a signal change which is produced only whensaid oscillation circuit is operating normally, and when saidoscillation circuit is a PUT oscillation circuit which uses a PUT forthe switching element, there is provided: a differentiating circuit fordifferentiating a cathode terminal voltage of said PUT; a photocouplercomprising a photodiode with an anode side connected to a constantvoltage line and a cathode side connected to an output terminal of saiddifferentiating circuit, and a phototransistor with a collector sideconnected via a resistor to an input signal line to which said inputsignal is applied, and an emitter side connected to said constantvoltage line; and a level conversion circuit comprising a capacitor anda diode with said capacitor connected between an intermediate pointbetween said resistor and said phototransistor and a cathode side ofsaid diode, and an anode side of said diode connected to said inputsignal line, and an output signal from said level conversion circuit ismade the output signal from said monitoring circuit.
 6. A fail-safetiming circuit characterized in comprising: an oscillation circuit whichproduces an oscillating ouput using the switching of a switchingelement, after the lapse of a previously set predetermined time fromafter applying an input signal; and a monitoring circuit for monitoringfor the normalcy of said oscillation circuit based on electricaloperating conditions of said oscillation circuit, and generating anoutput signal only when said oscillation circuit is normal; wherein saidmonitoring circuit monitors for the normalcy of said oscillation circuitbased on a sequential signal change in the various parts of saidoscillation circuit for when said oscillation circuit is operatingnormally, and when said oscillation circuit is a PUT oscillation circuitwhich uses a PUT for the switching element, there is provided: aphotocoupler comprising a photodiode and a phototransistor, fordetecting the presence of a gate current of the PUT of said oscillationcircuit; a voltage dividing circuit for dividing a cathode voltage ofsaid PUT; a transistor with an emitter side connected to a constantvoltage line and a collector side connected to a collector side of saidphototransistor, and a voltage divided by said voltage dividing circuitinput to a base terminal; and a level conversion circuit comprising acapacitor and a diode with said capacitor connected between anintermediate point between said transistor and said phototransistor anda cathode side of said diode, and an anode side of said diode connectedto said constant voltage line, and an output signal from said levelconversion circuit is made the output signal from said monitoringcircuit.
 7. A fail-safe timing circuit characterized in comprising: anoscillation circuit which produces an oscillating ouput using theswitching of a switching element, after the lapse of a previously setpredetermined time from after applying an input signal; and a monitoringcircuit for monitoring for the normalcy of said oscillation circuitbased on electrical operating conditions of said oscillation circuit,and generating an output signal only when said oscillation circuit isnormal; wherein said monitoring circuit monitors for the normalcy ofsaid oscillation circuit based on a sequential signal change in thevarious parts of said oscillation circuit for when said oscillationcircuit is operating normally, and when said oscillation circuit is aPUT oscillation circuit which uses a PUT for the switching element,there is provided: a first photocoupler comprising a first photodiodeand a first phototransistor, for detecting the presence of a gatecurrent of the PUT of said oscillation circuit; a second photocouplercomprising a second photodiode and a second phototransistor, fordetecting the presence of an anode current of the PUT of saidoscillation circuit; a voltage dividing circuit for dividing a cathodevoltage of said PUT; a transistor with an emitter side connected to aconstant voltage line and a collector side connected to a collector sideof said second phototransistor, and a voltage divided by said voltagedividing circuit input to a base terminal; and a level conversioncircuit comprising a capacitor and said first phototransistor with saidcapacitor connected between an intermediate point between saidtransistor and said second phototransistor and an emitter side of saidfirst phototransistor, and a collector side of said firstphototransistor connected to said constant voltage line, and an outputsignal from said level conversion circuit is made the output signal fromsaid monitoring circuit.
 8. A fail-safe timing circuit according toclaim 1, wherein said monitoring circuit monitors for the normalcy ofsaid oscillation circuit based on a sequential signal change in thevarious parts of said oscillation circuit for when said oscillationcircuit is operating normally, and when said oscillation circuit is aPUT oscillation circuit which uses a PUT for the switching element,there is provided: a photocoupler comprising a photodiode and aphototransistor, for detecting the presence of a gate current of the PUTof said oscillation circuit; a voltage dividing circuit for dividing acathode voltage of said PUT; a transistor with an emitter side connectedto a constant voltage line and a collector side connected to a collectorside of said phototransistor, and a voltage divided by said voltagedividing circuit input to a base terminal; and a level conversioncircuit comprising a capacitor and a diode with said capacitor connectedbetween an intermediate point between said transistor and saidphototransistor and a cathode side of said diode, and an anode side ofsaid diode connected to an input signal line, and an output signal fromsaid level conversion circuit is made the output signal from saidmonitoring circuit.
 9. A fail-safe timing circuit according to claim 1,wherein said monitoring circuit monitors for the normalcy of saidoscillation circuit based on a sequential signal change in the variousparts of said oscillation circuit for when said oscillation circuit isoperating normally, and when said oscillation circuit is a PUToscillation circuit which uses a PUT for the switching element, there isprovided: a first photocoupler comprising a first photodiode and a firstphototransistor, for detecting the presence of a gate current of the PUTof said oscillation circuit; a second photocoupler comprising a secondphotodiode and a second phototransistor, for detecting the presence ofan anode current of the PUT of said oscillation circuit; a voltagedividing circuit for dividing a cathode voltage of said PUT; atransistor with an emitter side connected to a constant voltage line anda collector side connected to a collector side of said secondphototransistor, and a voltage divided by said voltage dividing circuitinput to a base terminal; and a level conversion circuit comprising acapacitor and said first phototransistor with said capacitor connectedbetween an intermediate point between said transistor and said secondphototransistor and an emitter side of said first phototransistor, and acollector side of said first phototransistor connected to an inputsignal line, and an output signal from said level conversion circuit ismade the output signal from said monitoring circuit.
 10. A fail-safetiming circuit according to claim 1, wherein said monitoring circuitmonitors for the normalcy of said oscillation circuit based on asequential signal change in the various parts of said oscillationcircuit for when said oscillation circuit is operating normally, andwhen said oscillation circuit is a PUT oscillation circuit which uses aPUT for the switching element, there is provided: a photocouplercomprising a photodiode and a phototransistor, for detecting thepresence of an anode current of thePUT of said oscillation circuit; anda level conversion circuit comprising a capacitor and thephototransistor of said photocoupler, with one end of said capacitorconnected to an emitter side of said phototransistor which has acollector side connected to an input signal line, and a gate voltageapplied to the other end of said capacitor, and an output signal fromsaid level conversion circuit is made the output signal from saidmonitoring circuit.
 11. A fail-safe timing circuit according to claim 1,wherein said oscillation circuit is a one shot multi-vibrator.
 12. Afail-safe timing circuit characterized in comprising: an oscillationcircuit which produces an oscillating ouput using the switching of aswitching element, after the lapse of a previously set predeterminedtime from after applying an input signal; and a monitoring circuit formonitoring for the normalcy of said oscillation circuit based onelectrical operating conditions of said oscillation circuit, andgenerating an output signal only when said oscillation circuit isnormal; together with a self hold circuit with the input signal forinput to said timing circuit input to a first terminal, and the outputsignal from said monitoring circuit input to a second terminal, whichproduces an output signal when the input signals input to said first andsecond terminals are both higher than a power source potential, andwhich feeds back said output signal to the second terminal to self holdsaid output signal, and the output signal from said self hold circuit ismade a delay output signal.
 13. An on-delay circuit according to claim12, wherein an input signal line of said timing circuit and an inputsignal line to the first terminal of said self hold circuit are inseparate systems, and a resistance is disposed in at least one of theinput signal lines.